EDN

Sub-picofarad measurement with CMOS inverters

The inverters in a CMOS CD4069 can be used for both analog as well as digital applications. This Design Idea illustrates this by using all six inverters in a 4069 package to make a closed loop, ...
EDN

Flip-Flop Using CMOS NAND Gates

Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...
AZoNano

Direct-Write Fabrication of 1D Transistors and Non-CMOS Logic Gates: A Stimulus for Nanoelectronics to Mature

The transistor, an invention that heralded a new era in electronics, is the key component of practically all integrated circuits (ICs) and microprocessors. The point-contact transistor that Walter H.
Electronic Design

Simplified High-k/Metal-Gate Process Increases Planar CMOS Speed

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...
Design-Reuse

Low Power Universal Gates for Approximate Computing

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...
Nature

P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors

The Nature Index 2025 Research Leaders — previously known as Annual Tables — reveal the leading institutions and countries/territories in the natural and health sciences, according to their output in ...
Science Daily

Non-volatile bistable memory circuits for highly energy-efficient CMOS logic systems

Non-volatile bistable memory circuits pave the way for highly energy-efficient CMOS logic systems. Non-volatile bistable memory circuits being developed by Satoshi Sugahara and his team at Tokyo Tech ...
Electronic Design

Low Power, High Performance CMOS Logic

Scientists at the Tokyo Institute of Technology have developed low power, high performance CMOS logic technology that is vital to the future of microprocessors and system-on-chip (SoC) devices for ...
The Hindu

Nanomagnet assembly to make up efficient logic gate

A group at Indian Institute of Technology (IIT) Hyderabad has proposed a novel design methodology for constructing an adder logic gate using nanomagnets from magnetic quantum dot cellular automata. At ...