EDN

‘Wrap’ your cores to enable SoC test

Deep submicron technology enabled the design of the industry's first very large chips. The magnitude of the design effort involved in creating these chips led to the adoption of reuse methodologies ...
EDN

Design holds the key to cost-effective SOC testing

The most effective way to shorten test times is to test more of the SOC IP (intellectual-property) cores in parallel. However, for best results, the SOC design should anticipate parallel testing, and ...
Electronic Design

Tackling Next-Generation RF SOC Test

Developing an automated production test solution for current and next-generation complex RF SIP/SOC devices is an increasingly difficult task. Both the test program and the device interface board (DIB ...
Yahoo Finance

Advantest Unveils T2000 AiR2X Air-Cooled SoC and Power Analog Test Solution

T2000 AiR2X air-cooled SoC and power analog test solution · GlobeNewswire Inc. TOKYO, Dec. 11, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) ...
DIGITIMES

Advantest to boost SoC test equipment capacity to 5,000 units by 2027

Japan's Advantest has announced an acceleration of its capacity expansion plans for system-on-chip (SoC) test equipment in response to surging demand driven by artificial intelligence (AI) hardware ...
Nasdaq

Advantest Introduces Evolutionary V93000 EXA Scale™ SoC Test System

TOKYO, Sept. 23, 2020 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) has announced its next-generation V93000 testers targeted at advanced digital ...