EDN

How to improve FPGA-based ASIC prototyping with SystemVerilog

ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs. However, creating an ASIC is a high-investment ...
EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 2

The new SystemVerilog coding style is also easy to read and maintain compared to the Verilog method of modelling FSM's. Example 1. FSM Modelling with SystemVerilog. SystemVerilog also provides an ...
Design-Reuse

Development of Verification Environment for Layered Protocol using SystemVerilog

Today, functional verification consumes most of the time in the design of layered protocols like OSI Model, PCI Express, etc. As we think of reuse of design components, the reuse of verification ...
Design-Reuse

Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP

CAMPBELL, Calif. -- November 3, 2008--Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, under their IP Development Program - ...
NBC4 Columbus

Accellera Forms SystemVerilog Mixed-Signal Interface Types Working Group

ELK GROVE, Calif., Feb. 07, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.