Design-Reuse

A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SoC Designs

Complex system design requires modeling, testing, debug and analysis of many levels of abstraction with varying levels of accuracy. Reuse from previous steps is important at each step of the design ...
Design-Reuse

Transaction Recording, Modeling and Extensions for SystemVerilog

Adoption of transaction level modeling and the necessary tools for debugging and analysis has been slower than would be expected from growing SOC design sizes and complexities. This paper discusses ...
EDN

Consultant lauds Accellera’s role in SystemVerilog 3.1

ANAHEIM, Calif. — The Accellera standards organization is playing a crucial role in the development of SystemVerilog 3.1, according to language expert Stuart Sutherland, who spoke at a SystemVerilog ...
EDN

Getting in sync with UVM sequences

The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...